The present invention relates generally to memory devices, and more particularly, to a flash memory device with a variable erase pulse.
Electrically erasable and programmable read-only memory devices having arrays of what are known as flash cells, also called flash EEPROMs or flash memory devices, are found in a wide variety of electrical devices. A flash memory device is typically formed in an integrated circuit. A conventional flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate is floating or electrically isolated. The flash memory device has a large number of flash cells in an array where the control gate of each flash cell is connected to a word line and the drain is connected to a bit line, the flash cells being arranged in a grid of word lines and bit lines.
A flash cell is programmed by applying approximately 10 volts to the control gate, between 5 and 7 volts to the drain, and grounding the source and the substrate to induce hot electron injection from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming. The charge affects current in the channel region by determining the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
One type of flash memory device includes an array of multi-bit or multi-state flash cells. Multi-state flash cells have the same structure as ordinary flash cells and are capable of storing multiple bits of data in a single cell. A multi-bit or multi-state flash cell has multiple distinct threshold voltage levels over a voltage range. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell.
Data is stored in conventional flash memory devices by programming flash cells that have been previously erased. A flash cell is erased by applying an erase pulse of approximately xe2x88x9210 volts to the control gate, applying approximately 5 volts to the source, grounding the substrate and allowing the drain to float. In an alternate method of erasure the control gate is grounded and an erase pulse of approximately 12 volts is applied to the source. The electrons in the floating gate are induced to pass through the gate oxide to the source by Fowler-Nordheim tunneling such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced. The flash cell is then read in a manner described below to determine if it is erased. If the flash cell is not erased, another erase pulse is applied to the flash cell.
A flash cell is read by applying approximately 5 volts to the control gate, approximately 1 volt to the drain, and grounding the source and the substrate. The flash cell is rendered conductive and current between the source and the drain is sensed to determine data stored in the flash cell. The current is converted to a voltage that is compared with one or more reference voltages in a sense amplifier to determine the state of the flash cell. The current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
As flash memory devices age with use they tend to wear, or change physically, and their operational characteristics change. The operational efficiency of a flash memory device can decline over time due to these changes in its physical and operational characteristics. There remains a need for a flash memory device that may be operated efficiently over its entire operating life.
The above mentioned and other deficiencies are addressed in the following detailed description. A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase pulse to the flash cell, and reading the flash cell. For each time the flash cell is read and is not in an erased state, the method includes applying a short erase pulse to the flash cell, counting the short erase pulse, and reading the flash cell. Finally, a length of the long erase pulse is adjusted based on the counted number of short erase pulses that were applied to the flash cell. The length of the long erase pulse may be increased if the counted number of short erase pulses is more than a high number of pulses, or it may be decreased if the counted number of short erase pulses is less than a low number of pulses. The length of the long erase pulse may be adjusted based on a past average of short erase pulses applied to the flash cell, or a quantity representing short erase pulses applied to the flash cell over a selected number of prior erases of the flash cell. The flash memory device may have a control circuit with elements to implement the method.
Advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description.